Multiplying digital-to-analog converters (MDACs) are commonly used in pipelined analog-to-digital converters (ADCs). MDACs in this application generally employ switched capacitive networks and an MDAC amplifier. Turning to FIG. 1 of the drawings, a simplified, conventional MDAC amplifier with its associated capacitors can be seen. Here, an input signal VIN is applied to sampling capacitor CS (which is coupled to the inverting terminal of MDAC amplifier 102). Additionally, feedback capacitor CF is coupled between the output terminal of amplifier 102 and the inverting terminal of amplifier 102. Assuming that amplifier 102 has a good phase margin, its output would settle like a single pole system as follows:
                    VOUT        =                  VIN          *                      CS            CF                    *                      (                          1              -                              ⅇ                                                      -                    t                                    τ                                                      )                                              (        1        )            Of interest, however, is the output voltage VOUT at setting time of the amplifier 102
      (          t      ≈                        T          s                3              )    ,where TS is the clock or sample period of the ADC, so that equation (1) becomes:
                    VOUT        =                  VIN          *                      CS            CF                    *                                    (                              1                -                                  ⅇ                                                            -                                              T                        S                                                                                    3                      ⁢                                                                                          ⁢                      τ                                                                                  )                        .                                              (        2        )            
This results in an error of:
                    e        =                  VIN          *                      CS            CF                    *                                    ⅇ                                                -                                      T                    S                                                                    3                  ⁢                                                                          ⁢                  τ                                                      .                                              (        3        )            Thus, it can clearly be seen that this error shown in equation (3) increase exponentially with the decrease in the period of the ADC clock TS. Therefore, there is a need to address this error.
Some other conventional circuits are: U.S. Pat. No. 6,323,800; U.S. Pat. No. 6,573,791; U.S. Pat. No. 7,230,483; U.S. Pat. No. 7,397,409; U.S. Patent Pre-Grant Publ. No. 2006/0197593; and U.S. Patent Pre-Grant Publ. No. 2009/0146854.